1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly to a semiconductor device having a damascene structure and a method of manufacturing the same.
2. Description of the Related Art
In connection with enhancement in the integration of semiconductor devices and reduction in chip size, miniaturization of wires and multi-layered wiring have been recently promoted. As a method of forming a multi-layered wiring structure is generally carried out a so-called damascene process in which Cu is embedded into via holes and wiring trench patterns at the same time and then surface flattening is carried out by using CMP (Chemical Mechanical Polishing) method to form wires. With the damascene process described above, the density of the wiring pattern can be increased, however, a wiring delay problem would occur due to the parasitic capacity between wiring patterns if the wiring patterns are close to each other. Therefore, it is an important object to reduce the wiring capacity for an improvement in wiring delay.
As a method to reduce the wiring capacity is considered a method of using material having a lower dielectric constant as an interlayer insulating film in place of a SiO2-based insulating film which has been hitherto used (See JP(A)-2000-77409, etc.). Here, a conventional damascene process using low dielectric constant film as an interlayer insulating film will be described with reference to the accompanying drawings. FIGS. 23A to 25C are cross-sectional views showing a via-first process corresponding to one type of conventional damascene process.
First, as shown in FIG. 23A, a first etching stop film 7 preventing diffusion of Cu and serving as an etching stopper for via holes, a first interlayer insulating film 6 of SiO2, a second etching stop film 5 serving as an etching stopper for wire trench patterns, a second interlayer insulating film 4 serving as a low dielectric constant film and a cap insulating film 3 of SiO2 are successively deposited on a wire substrate 8 on which a lower layer wire of Cu or the like is formed by a well-known method. Further, a first antireflection coating (ARC: Anti Reflection Coating) 2a and a photoresist are successively coated, and then subjected to light-exposure and development treatments to form a first resist pattern 1a for formation of the via holes 9.
Subsequently, as shown in FIG. 23B, the first antireflection coating 2a, the cap insulating film 3, the second interlayer insulating film 4, the second etching stop film 5 and the first interlayer insulating film 6 are successively etched with the first resist pattern 1a being used as a mask by using a well-known dry etching technique to form a via hole 9 penetrating through these films. Thereafter, by carrying out an oxygen plasma ashing treatment and a wet treatment using organic peeling liquid, the first resist pattern 1a and the first antireflection coating 2a are peeled off stripped off or removed and the residual materials of the dry etching are removed.
After the wet treatment using the organic peeling liquid, as shown in FIGS. 23C and 24A, a second antireflection coating 2b and a photoresist are successively coated, and then subjected to light-exposure and development treatments to form a second resist pattern 1b through which the wire trench patterns are etched (see FIG. 24B). Thereafter, by using a well-known dry etching technique, the second antireflection coating 2b, the cap insulating film 3 and the second interlayer insulating film 4 are successively etched to form wire trench patterns 10. Thereafter, by using the oxygen plasma ashing and the wet treatment using the organic peeling liquid, the second resist pattern 1b and the second antireflection film 2b are peeled off, and the residual materials of the dry etching are removed (see FIGS. 24C, 25A, 25B). A wiring material 11 of Cu or the like is embedded in the wire trench patterns 10 and the via holes 9 and the surface thereof is flattened by the CMP method to form a dual damascene structure.
Reference is made to the description at pages 5 to 7 and FIG. 1 of the above JP(A)-2000-77409.
As described above, according to the via-first dual damascene process, the via holes 9 are formed by using the first resist pattern 1a, and after the first resist pattern 1a is peeled off, the second resist pattern 1b for etching the wire trench patterns 10 is subsequently formed. However, in the conventional method, after the wet peeling process using the basic organic peeling liquid for peeling the first resist pattern 1a and the first antireflection coating 2a and before the coating of the second antireflection coating 2b or the resist, no pre-treatment is carried out, or dehydrating bake (for about 2 minutes at a temperature of about 150° C. to 250° C.) or thinner pre-wetting is merely carried out as a pre-treatment by a coating machine.
The dehydrating bake and the thinner pre-wetting treatments aim to remove water adsorbed on the substrate, particularly the inner wall of the via holes 9, and they do not aim to remove materials disturbing the chemical reactions in the resist such as basic materials, etc. (hereinafter referred to as reaction inhibiting materials). Therefore, there is a problem that the resolution of the second resist pattern 1b is lowered by the reaction inhibiting materials. That is, the chemical reactions are promoted by using acid catalyst occurring in the resist through the light exposure so that the resist is partially made to be easily dissoluble by developing liquid, thereby forming a resist pattern. However, the reaction inhibiting materials infiltrating into the interlayer insulating film exudes into the resist to deactivate the acid catalyst and thus suppress the chemical reactions in the resist, so that the resist at a part of the wire trench patterns 10, particularly the resist in the neighborhood of the via holes 9 is not sufficiently removed and thus remains there.
If the wiring trench patterns are subsequently etched under the state that the resist remains at the portion to be originally removed, the wire trench patterns 10 get out of shape, or particularly when a large part of the resist remains as shown in FIG. 24B, etching residue called as crown 15 as shown in FIG. 25A remains around the via holes 9. The crown 15 is not dissolved in the organic peeling liquid, and thus it remains until the wiring material 11 is embedded. Therefore, there occurs a problem that reliability of the completed wires is reduced.
This problem also occurs when SiO2 is used for the interlayer insulating film, and it occurs more remarkably when a low dielectric constant film is used for the interlayer insulating film. Since the low dielectric constant film is generally formed of coarse film, it is designed so that chemical solution such as organic peeling liquid, cleaning liquid, etc. is liable to infiltrate into the inside of the film and floating substances in air are liable to adhere to the film. Therefore, when antireflection coating or resist coated on the film concerned is baked, reaction inhibiting materials contained in the chemical solution exude gradually from the film concerned into the resist.
It is also known that, in addition to the chemical solution such as organic peeling liquid, cleaning liquid, etc., specific elements in the interlayer insulating film function as the reaction inhibiting materials. Therefore, if formation of the resist pattern is performed under such a condition that the interlayer insulating film or the etching stop film is exposed to the inner wall of the via-hole or the wiring trench pattern formed therein, the same problem as mentioned in the above occurs.
This problem occurs not only in the via-first dual damascene process, but also in other damascene processes such as a dual hard mask process, trench-first dual damascene process, etc. or in another semiconductor process having a step of forming a next resist pattern after a wet treatment using organic peeling liquid, cleaning liquid or the like or forming a resist pattern under such a condition that the insulating film is exposed to the inner wall of the via-hole or the trench pattern.